Number of pipe on X1700

[rem5]

Hi,

I'm running latest GIT for drm, mesa, radeon driver with xserver 1.4.99.902.

Everything works nicely (xv, 3d, composite) and just one hard lockup with xv so far, but one question : is this line OK in log for a X1700 ? :

(II) RADEON(0): num pipes is 1

shouldn't it be greater than 1 ?

for entire log : http://pastebin.com/m7ac89794


And another little question : have you got any idea when Page Flipping will be enabled in r500 ?


Thank you for all your hard work :)

[Execute_Method]

(II) RADEON(0): num pipes is 1

shouldn't it be greater than 1 ?



I have an x1650 and noticed the same thing. I was just thinking about it this morning, but I'm too happy that I have 3d to care too much.

+1 keep up the good work and fight hard the good fight.

Open Source FTW

[bridgman]

If it's referring to the number of "quad pipes" (almost all of our chips from r300 on are built using one or more quad pipe blocks) then it probably is correct. Internally we talk about th R300 as a "2 pipe" chip, ie 2 quad pipes, and the X1650 would be a single pipe chip (except it has 3 times as many ALUs as an X1300).

Hopefully someone who knows the code will jump in here and confirm. The programming docs and register specs we released definitely talk about 1,2,3 or 4 papes -- not 4, 8, 12 or 16.

[agd5f]

If it's referring to the number of "quad pipes" (almost all of our chips from r300 on are built using one or more quad pipe blocks) then it probably is correct. Internally we talk about th R300 as a "2 pipe" chip, ie 2 quad pipes, and the X1650 would be a single pipe chip (except it has 3 times as many ALUs as an X1300).

Hopefully someone who knows the code will jump in here and confirm. The programming docs and register specs we released definitely talk about 1,2,3 or 4 papes -- not 4, 8, 12 or 16.

That's correct.

[rem5]

thank you for the explication !