New Maintainer Steps Up For GCC Compiler's MIPS CPU Port

[phoronix]

Phoronix: New Maintainer Steps Up For GCC Compiler's MIPS CPU Port

With development of the MIPS architecture having officially ended two years ago in favor of focusing on RISC-V for future CPU designs and the overall decline of that CPU architecture, it's been years since the GNU Compiler Collection (GCC) has seen its MIPS code well maintained. However, now a capable developer has stepped up willing to serve as the GCC maintainer for MIPS...

https://www.phoronix.com/news/GCC-MIPS-New-Maintainer

[ayumu]

Some context: MIPS (the company) has adopted the industry standard RISC-V, thus MIPS (the ISA) is officially legacy.

In contrast with x86 and arm, which are de-facto legacy instead of officially.

[stormcrow]

Some context: MIPS (the company) has adopted the industry standard RISC-V, thus MIPS (the ISA) is officially legacy.

In contrast with x86 and arm, which are de-facto legacy instead of officially.

More accurately officially deprecated by its original caretaker. Legacy doesn't mean obsolete. It simply means it's been handed down over time. Legacies can evolve to remain useful. Deprecated means MIPS has obsoleted its MIPS ISA and won't be updating it any longer. The PRC internally standardized on MIPS and MIPS-like architectures so they're internalizing its upkeep. I wasn't surprised to see the name who stepped up to maintain GCC for MIPS. The Western nations would likely do the same thing with x86 should Intel ever decide to deprecate it like they once tried to do in the early naughts. They've already done so for obsoleted IBM mainframes still in use and slowly being moved to emulated containers.