The AVX-512 Performance Advantage With AMD EPYC Bergamo

[phoronix]

Phoronix: The AVX-512 Performance Advantage With AMD EPYC Bergamo

While this week was the surprise announcement of Intel AVX10 and with that taking the super-set of AVX-512 to both E and P core processors in the future, for next year's Xeon "Sierra Forest" server processors at up to 144 ocres, it appears they will lack AVX-512/AVX10. Intel's AVX10 announcement noted initial support with Granite Rapids processors that will debut next year but no mention of the E-core-only Sierra Forest. With the AVX10 only coming to P/E core client processors after Granite Rapids, it would appear the high density Sierra Forest generation will miss out on AVX10/AVX-512 and not appear until Clearwater Forest. Meanwhile with the 128-core AMD EPYC "Bergamo" processors now shipping, there is AVX-512 with the Zen 4C cores. Here are some benchmarks looking at the AVX-512 impact for Bergamo.

https://www.phoronix.com/review/epyc-bergamo-avx512

[bridgman]

at up to 144 ocres

in both forum post and article.

My first thought reading it was "144 acres... damn that's a big chip".

[Michael]

in both forum post and article.

My first thought reading it was "144 acres... damn that's a big chip".

Heh fixed, thanks!

[Snaipersky]

Talk about silicon greenfield!

[aviallon]

Double the performance. Damn.

[jochendemuth]

Phoronix: The AVX-512 Performance Advantage With AMD EPYC Bergamo
While this week was the surprise announcement of Intel AVX10 and with that taking the super-set of AVX-512 to both E and P core processors in the future, for next year's Xeon "Sierra Forest" server processors at up to 144 cores, it appears they will lack AVX-512/AVX10.
https://www.phoronix.com/review/epyc-bergamo-avx512

Looks like Intel recognized another time they shot themselves in the foot. AMDs clever move of adding AVX512 to all cores exposed Intels strategy to extract premium dollars for this feature set (requiring upgrade to professionally priced Xeon chips) from customers and made it no longer viable.

The jury is still out on the other strategy (more same cores more better vs. accelerators) but I think the simplicity of coding to a common feature set and deploying to a common feature set will win over the strategy of licensing accelerators baked into already paid-for chips.

Intels announcement is cleverly designed to spread FUD asking customers to wait until future chips can fix Intels strategic mistakes.

[paulocoghi]

It seems this:

But with a 51 Watt average and 74 Watt peak

should be:

But with a 51 Celsius average and 74 Celsius peak

[Michael]

It seems this:



should be:

Yep thanks

[ayumu]

While Intel's pushing their AVX10, APX and x86-S nonsense, I am hopeful AMD will respond with a new generation of Zen cores that boot into native RISC-V and provide x86 acceleration for unprivileged programs.

AMD leads market share. The opportunity to move the mainstream off x86 is finally there.

Otherwise, it will have to be bottom up, starting with RISC-V netbooks running Windows for RISC-V from other vendors such as Qualcomm. We know Windows is a thing as of RISC-V Summit in December.

[brucethemoose]

While Intel's pushing their AVX10, APX and x86-S nonsense, I am hopeful AMD will respond with a new generation of Zen cores that boot into native RISC-V and provide x86 acceleration for unprivileged programs.

AMD leads market share. The opportunity to move the mainstream off x86 is finally there.

Otherwise, it will have to be bottom up, starting with RISC-V netbooks running Windows for RISC-V from other vendors such as Qualcomm. We know Windows is a thing as of RISC-V Summit in December.

... I don't think this is possible. Even if its technically doable to "switch" between RISC V and x86 at boot, which seems questionable given the ISA/extension differences, I don't think you run them simultaneously.

And even if thats possible, AMD has no economic incentive to tape out a RISC-V processor. Their x86 license is a very profitable moat, and RISC-V is very finicky to actually use outside of embedded stuff.

If we are very, very lucky, someone will tape out Tenstorrent's RISC-V core for cloud use.