Fedora Now Has Bootable RISC-V Disk Images Available

[phoronix]

Phoronix: Fedora Now Has Bootable RISC-V Disk Images Available

Fedora has been making a lot of RISC-V build/packaging progress over the past few months while this weekend the milestone was announced that they are hosting clean, RPM-built, bootable disk images for this open-source RISC-V instruction set architecture...

http://www.phoronix.com/scan.php?page=news_item&px=Fedora-RISC-V-Bootable-IMG

[c117152]

Nice! Let me just boot it... Oh. Aww...

[microcode]

Nice! Let me just boot it... Oh. Aww...

Patience, c117152, patience.

Without software, it's hard to justify shipping hardware.

[bridgman]

Nice! Let me just boot it... Oh. Aww...

AFAIK there is a reference ISA simulator plus a version of QEMU with RISC-V emulation. I believe QEMU was used for the porting/bootstrapping effort.

[darkbasic]

Patience, c117152, patience.

Without software, it's hard to justify shipping hardware.

It seems we have the software now, can't wait to test

[cjcox]

I'd wait a few versions... of course that could be RISC-Y

[timofonic]

I'd wait a few versions... of course that could be RISC-Y

I'll prefer RISC-Z, using qbits and memristors.

Is [https://riscv.org/wp-content/uploads...tory_V2.pdf]NV RISC-V[/url] a proprietary fork of RISC-V by Nvidia? I'm sure they orgasmically love proprietary stuff.

So RISC-V is like BSD software massively cannibalized by corporate projects like PlayStation4 (and extremely modified, of course), but for hardware. I see these companies are going to provide a great feedback once they deploy and massively customize this free "IP" on their proprietary hardware with proprietary firmwares

RISC-V sponsorship is full of BIG GUYS,

The RISC-V ISA is incomplete, but the user-mode specification indicates that it’s quite promising. The clean architecture is easier to implement than ARM, specifically owing to simpler decoding. ARMv8 currently requires de coding of three different ISAs: ARMv8, ARMv7, and Thumb. In addition, RISC-V offers simpler addressing modes than ARM and omits complex instructions such as load/store multiple. This distinction is certainly noticeable; the Rocket core is roughly half the size of a similar ARM core.

But the choice of ISA has a minimal effect on a larger core (e.g., three-issue out-of-order CPU), especially once caches are considered:.

- For example: Intel’s x86 CPUs, which require complex decoders, are similar in overall size to RISC cores of comparable performance.
- Even for scalar micro-architectures, the die-area benefits of RISC-V are less significant when compared to a simpler RISC ISA such as ARC or MIPS]

RISC-V’s greatest technical promise is the flexibility of custom extensions combined with a general-purpose architecture. Potential RISC-V extensions include Cray style vector extensions, transactional memory, and bit manipulation.

Both ARC (now Synopsys) and Tensilica (now Cadence) have offered similar extension capability for years: Custom extensions can deliver huge performance gains, but they require custom tool chains, and they limit software portability.

The RISC-V software ecosystem is in the early stages.

- A Linux 4.1 branch has been ported.

- Yocto: A full embedded Linux distribution.

- The RISC-V tool chain includes: GCC, LLVM and Clang, GDB, a verification suite, and several simulators.

But the most important milestone is completing the supervisor interface (SBI), which will standardize the environment for Linux and BSD operating systems and thereby deliver the general purpose aspect. Mainstream OS support will broaden the appeal of RISC-V and enable many more applications.

On the basis of early developments, the RISC-V ISA appears promising: It offers all the basic RISC features with a few twists that simplify the implementation, thereby reducing die area and potentially power consumption. Compared with today’s two most popular ISAs, RISC-V offers considerable area savings, particularly for low-end designs, and the ability to add custom extensions. [b]Compared with ISAs such as ARC and Tensilica, RISC-V offers fewer technical advantages, but its open-source business model will continue to drive interest in the new ISA.[/url]

All I see here is resumed in a world: PROMISES.

Show me the real thing running in real hardware competing latest and best iterations of Power, ARM, MIPS, X64 and others. Will we able to see supercomputers using RISC-V? I doubt it, big guys are the ones moving the project to their own interests and that will be to make alternate platforms to FAIL or at least just limited success in certain nichos.

What about Sunway? It's inspired by DEC Alpha and used by Military Chinese. The SW26010 model seems quite promising and used in China TOP500 supercompiuter

What about POWER9?

The United States Department of Energy together with Oak Ridge National Laboratory and Lawrence Livermore National Laboratory have contracted IBM and Nvidia to build two supercomputers, the Summit and the Sierra, that will be based on POWER9 processors coupled with Nvidia's Volta GPUs. These systems are slated to go online in 2017

[microcode]

I'll prefer RISC-Z, using qbits and memristors.

Is [https://riscv.org/wp-content/uploads...tory_V2.pdf]NV RISC-V[/url] a proprietary fork of RISC-V by Nvidia? I'm sure they orgasmically love proprietary stuff.

So RISC-V is like BSD software massively cannibalized by corporate projects like PlayStation4 (and extremely modified, of course), but for hardware. I see these companies are going to provide a great feedback once they deploy and massively customize this free "IP" on their proprietary hardware with proprietary firmwares

RISC-V sponsorship is full of BIG GUYS,




All I see here is resumed in a world: PROMISES.

Show me the real thing running in real hardware competing latest and best iterations of Power, ARM, MIPS, X64 and others. Will we able to see supercomputers using RISC-V? I doubt it, big guys are the ones moving the project to their own interests and that will be to make alternate platforms to FAIL or at least just limited success in certain nichos.

What about Sunway? It's inspired by DEC Alpha and used by Military Chinese. The SW26010 model seems quite promising and used in China TOP500 supercompiuter

What about POWER9?

For what it's worth, the government of India seems pretty dead-set on deploying the five or so families of RISC-V chips they've designed and tested. Maybe soon we'll see what their server chips perform like. NVIDIA has it in the next or next next generation of discrete and embedded GPUs they will ship. SiFive has a promising deep-embedded platform, and maybe a promising high performance platform in the works.

I think there's enough momentum going that we'll see more than "promises".

[CrystalGamma]

What about Sunway? It's inspired by DEC Alpha […].

Looking at the spec, so is RISC-V …

[milkylainen]

No ******* hardware.
And no hardware is because hardware is a P.I.T.A.
I have seen and worked with various "open" hardware implementations of CPU's.
They _all_ sucked bigtime. Including the OpenRISC and their sorry state some 15 years after inception.
Implementing a CPU that won't be a useless piece of crap with todays measurements, will require some serious amount of work.
Nobody is willing to put down that work and release it for free.

Nvidia, IBM etc etc. All are watching to see where this is going. Nobody is going to chip in with resources.