It's only 2.5Wp.
https://en.wikipedia.org/wiki/Project_Denver I wouldn't be surprised if more ARM partners tried their hand at desktop/server AA64 parts(AMD has already announced they'll be working on ARM Opteron parts).
I don't understand cpu archtecture enought, maybe you guys will help clarify. How much o the CPU modern CPU archtecture is linked to the ISA? I mean, would it take too much work to say port Piledriver/Steamroller/Excavator to accept ARM ISA? Would the same apply to Haswell/Broadwell/etc? ARM is constantly bashed by being too low performance, but does the performance has anything to do with the ISA or is it simply because nobody has released a high power ARM chip yet?
The way I see it, its not about technology, it's abou business model. ARM business model allows for the creation of an infinite number of SoCs with different building blocks that all run the same Apps. x86 does not. If you are writing x86 Apps you are bound to run on the limited range of chips sold by Intel and AMD, so in the long run, ARM is a no-brainer simply due to the sheer variety and innovation possible in the ARM space, as long as they keep fragmentation in check.
In view of the above, I'm very curious to know if we can expect something like a 125W Steamroller ARM chip in the near future. With everybody but intel on the ARM bandwagon, I can't see Intel's big custumers being very happy having a single supplier...
How is the install trivial? Did anybody read the instructions? It is a lot of steps, just to get something with broken sound, no hardware acceleration, and a broken touchpad. And, where, in order to persist it, you need to type a tricky command.
Oh well, the CPU performance per watt seems stellar. It would be nice to plot that! (something like a geometric mean of performance in all tests/ normalized to processor's TDP)
But the A6 is about equivalent to what Qualcomm was shipping for a year with their Krait-based Snapdragon S4s.
And there's no way an A6 is in the same league as a Cortex-A15 anything.
Still the same crap i see. The difference is very simple. "Complex" and "Reduced" are not for instructions but for instruction sets. So its Complex or Reduced relations between instructions. So on RISC one instruction is a little the other or continuation of another or other relation. On CISC instructions don't have the same root not even when they divide to Micro-Ops or compress to Macro-Ops, that's only possible with recompiling. The thing is that on RISC the instructions run instantly and all possibilities together in a single vector. On CISC they need extended Microcode, many units, and there is not possibility for JIT-streaming, like graphics because the CISC compiler cannot use all the units efficiently, wile with RISC any data can co-execute with any data. At the end the only difference is that for the same generation and possibilities, RISC needs 1/10 the transistors to do the same amount of work and the 1/10 Watts.
quite easily beats both the A15 and S4 in GPU benchmarks. But perhaps these are a flub too?