ymmd! :D .Quote:
Originally Posted by mark45
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ymmd! :D .Quote:
Originally Posted by mark45
ARMv8 chips will also have 10x faster cryptography than current ARM chips.
NO they do not! The code to execute these older instructions is moved OUT of the core and into microcode so the older instructions can be emulated using the new core. Thus the core can be clean of the old architectural decisions.Quote:
Originally Posted by uid313
HOW do you think Intel has managed to keep up performance while maintaining compatibility with 8086? Do you honestly assert that all our modern Intel CPUs are carrying around an 8086 core so they can execute those instructions? NO, they are executed in microcode.
BESIDES ALL OF THIS, the actual instruction set executed by the core has ZILCH to do with the instruction set exposed to software. When your code is executed on a modern CPU the instructions are pipelined and re-ordered and re-written and the code executed by the core is NOT THE SAME as the code you wrote. So the API you see, even from assembly language, is all just an abstraction anyway. The Intel 32-bit instruction set runs on both Pentium Pro and on Ivy Bridge despite the fact that those two processors have very very little in common.
You really have to ask if "legacy baggage" has any relevance when it has no practical meaning. IBM mainframes are still emulating the 360 instruction set from the 1970's and yet they are not slowed down. Heck your modern IBM mainframe is emulating about a dozen different old IBM architectures and it does it all without slowing down modern code by even a cycle. IBM Mainframes? you mean those systems that have been running linux in a VM environment long before Intel?
"Reduced Instruction Set" means increased code size. Instructions that carry less information mean that you need more of themQuote:
Originally Posted by uid313
CISC actually does quite well performance wise because one of the execution bottlenecks is the fetching of instructions. When you use long winded RISC instructions you have more code and more read cycles to fetch your big code from slow RAM.
The ideal instruction set is Hoffman-encoded CISC where the often used instructions are very short and the little-used instructions are longer. This maximizes the available memory bandwidth.
And AGAIN since the instruction set is just an abstraction and has NOTHING to do with the actual hardware you might as well shoot for performance. Who cares about that dreadful CISC code? Nobody is ever going to look at it. It shoots out of the compiler and into the instruction unit and nobody needs to actually look at it or appreciate its intrinsic beauty.
It still makes chips bigger, more complex, more expensive, hotter and consume more.Quote:
Originally Posted by frantaylor
Anyway, AES-NI and similar instructions make it easier to plant backdoor.
All right, I use encryption under LVM on a Pentium B940 laptop. Now it will run faster! Oh, wait, no it won't, Intel fused off AESNI and AVX on this chip. *middlefinger* to you Intel.
Err, you bought a reduced feature set processor and you're angry that it doesn't provide the full set of features? What kind of sense does that make?Quote:
Originally Posted by willmore
Because they have a business model based on non-reality based feature differientation? Does AMD do that?Quote:
Originally Posted by Gusar
How does this answer my question? You bought a processor with a known feature set. If this set is not sufficient for your needs, you shouldn't have bought that processor.Quote:
Originally Posted by willmore
From what I know, no. But why didn't you buy AMD then?Quote:
Originally Posted by willmore
Seems to me you didn't do enough research before making your purchase. If that's correct, this one is on you and only on you, and it makes no sense to be angry at Intel.
I never said it was insufficient for my needs. I said that it could have performed better. I'm sorry that you can't understand why a consumer would be unhappy with Intel and their business practices.Quote:
Originally Posted by Gusar