You are partially correct. QuickPath is the replacement for *part* of the functions of the FSB. The Nehalem is exactly like AMD K8 and K10 setups. Every Nehalem CPU has an integrated RAM controller that talks *directly* to memory, just like K8s and K10s. QuickPath serves the same purpose as HyperTransport, which is to talk to the chipset and in multiple-socket setups, to talk to other CPUs. So:
Originally Posted by karthikrg
- In a single-socket setup, all data from memory goes directly to the CPU. The QuickPath interface does NOT carry information from RAM to the CPU. It merely allows for communication between the CPU and the chipset.
- In a multi-socket setup, you have a non-uniform memory access (NUMA) arrangement as you have your data spread over two or more independent banks of RAM. If you are CPU 0 accessing data from RAM attached to CPU 0, no data travels over the QuickPath link. If you are CPU 1 trying to access the same information, then you have to go over the QuickPath link to use CPU 0's memory controller to get the data from its RAM bank.
If Intel decides to pitch QuickPath in favor of PCI Express, it will ONLY affect multi-socket setups. (And they will not ditch QPI for socket-to-socket communication as data from RAM *does* travel over that link.) No data from RAM ever travels to the CPU over QuickPath in a single-socket setup and the CPU<->chipset link is a relatively low-bandwidth one, so going to PCIe there is no big deal. In fact, AMD is going from HyperTransport to PCIe for the CPU-to-chipset link in their upcoming mobile processors, meaning that those chips will have NO HT links at all. It will make no difference in performance.