AMD's RS880 / 785G Gains Open-Source Acceleration

[phoronix]

Phoronix: AMD's RS880 / 785G Gains Open-Source Acceleration

Back in March we shared that the open-source ATI driver had gained support for the unreleased ATI RS880 IGP. Well, the RS880 ended up being turned into the 785G due to some problems on AMD's side, but today this new, much more powerful IGP has launched...

http://www.phoronix.com/vr.php?view=NzQyOQ

[bridgman]

Alex has also submitted a drm patch to the dri-devel mailing list. I suspect that this patch will also be required for rs880/785G support :

http://marc.info/?l=dri-devel&m=124939979703242&w=2

[Pfanne]

hell yeah!
launch day oss support

[Louise]

Amazing how much work that is being commited these days.

In just 2 weeks, have we got KMS and Compiz for R600+R700, and 2D for an unreleased IGP.

[b4283]

wait, in the article claim this acceleration is in xf86-video-ati for 780G ?

isn't this suppoesd to be in radeonhd ?

[Louise]

Reading the many reviews at AMDzone.com

http://www.amdzone.com/index.php/new...oards-pictured

http://www.amdzone.com/index.php/new...hipset-reviews

I tend to wonder, why the South bridge isn't integrated in the North bridge? Wouldn't that be cheaper?

[nanonyme]

wait, in the article claim this acceleration is in xf86-video-ati for 780G ?

isn't this suppoesd to be in radeonhd ?

Now, what makes you say that? They both are supposed to support all the newest (radeon) cards.

[b4283]

Now, what makes you say that? They both are supposed to support all the newest (radeon) cards.

yeah, i know that. but sometimes i'm confused by articles that convince me -ati has better support than -radeonhd.

i've used both on my 780G, but didn't find any differences though. (maybe in the Xv accelerations?)

[bridgman]

We weren't sure when the 785G was going to launch. I noticed the announcement this morning so Alex pushed out what he had ready, which was radeon. The radeonhd driver should need pretty much the same changes.

Louise, as I understand it if you put a typical wide-bus Northbridge and Southbridge in the same package the pin count gets too high to be practical. There are very few connections between NB and SB, so you don't save much in pins by combining them.

There also used to be a requirement for different processes to handle the more analog-y functions on SB, not sure if that is still a factor.

[Louise]

Louise, as I understand it if you put a typical wide-bus Northbridge and Southbridge in the same package the pin count gets too high to be practical. There are very few connections between NB and SB, so you don't save much in pins by combining them.

There also used to be a requirement for different processes to handle the more analog-y functions on SB, not sure if that is still a factor.

I had no idea that the pin count also were an issue for chipsets...

Let's hope that "16 cores is enough for anyone" That's at least what I have read is the max possible CPU cores.

Maybe we will see pins sticking out of the sides that goes directly into the ram modules? 4 sides => 4 memory banks.

I read that using optics (lasers) instead of electrical pins are 15-20 years out in the future, as mirrors that are able to change state can only operate at MHz right now.

Using lasers inside a CPU would come sooner. The problem here was the size of the emitters, where they are measured in microns.