CRTC virtual pixel clock in displayport mode, and atombios SetPixelClock
In displayport mode, the DCPLL defaults to 600MHz for DCE4 and 540MHz for DCE5.
When programming the video mode for a crtc, SetPixelClock command table is used.
What are the parameters really used for this command table to program the crtc virtual pixel clock (as stated in radeon_atom_pick_pll)?
I did a bit of testing and, with a zeroed param struct, only the pixel clock field, the crtc id field and the pll_id field seem to be relevant for crtc virtual pixel clock programming.
Am I right or the PLL parameters/transmitter id must be used?