Originally Posted by pvtcupcakes
"Sehr hohe SPEC-Performancewerte, hohe Energieeffizienz"
high SPEC points and High speed per WATT
4 socket version: "759 SPECint_rate2006 und 621 SPECfp_rate2006"
"Unter Volllast mit SPECjbb2005 beschränkt sich das Opteron-6170-Testsystem auch auf 376 Watt "
max power consuming: 376watt
idle : 132 watt
for desktop use : http://www.lantronic-it.de/product_i...8SGL-SG34.html
Originally Posted by crazycheese
single socket G34 supermicro board 273€
and : http://geizhals.at/a508671.html
AMD Opteron 6128, 8x 2.00GHz, 80 watt TDP 273€
yes not cheap but the most Performance per Watt
A small but important point here: a a dual-core processor is not twice as fast as a single core. It can be UP TO twice as fast (minus a certain amount for the overhead of managing both cores) but only if the task being performed can be parallelised and the program has been parallelised, even then, it needs to be done properly. I believe the overhead increases with the number of cores.
Originally Posted by crazycheese
Some problems are trivial to parallelise, others are impossible, so be careful when making the "(time taken by a single core) / (number of cores)" assumption for parallel processing.
Also, a core that is "sleeping" doesn't necessarily consume trivial power (particularly if it's on the same die as cores that are working), and it doesn't necessarily take a trivial amount of time to get in/out of a sleep mode (e.g. you might need to wait for PLLs to lock, caches to flush/fill, etc.).
this is wrong because there are Super-linear-speedup-cpus..
Originally Posted by archibald
2 cores is faster than 2 single cores and 4 cores are faster than 5 or 6 single cores and 8 cores are faster than 12 single cores and so one.
and Amdahl's law is refuted http://en.wikipedia.org/wiki/Amdahl%27s_law
because of the Super-linear-speedup-effect
the Opteron 6000 is a Super-Linear-Speedup CPU thats because 1 core can use the L3 cache of all other cores!
so all 48 cores have 48mb of L3 cache! and 1 single theat can use this cache!
the opteron 6000 is also superlinear because 1 core can use all ram channels of all other cores !
so an opteron 6000 48 core system do have 16 channel ram !
You are naively wrong. Opteron doesn't work that way. A single die will only have 6 cores. The rest are connected in HT mesh just like multi socket systems. Your non-linear scale is up to 6 cores for now. Please no more rocket speed jokes
Amdahl's law is valid independently of the machine architecture. The architecture can impose serialization in some cases, but what really matters is the algorithm. You can't turn an inherently serial process (e.g. a naive bytecode interpreter fetch/decode/execute loop) into a parallel one merely by changing the host CPU.
"You are naively wrong. Opteron doesn't work that way."
Originally Posted by FunkyRider
LOL you are just outdated
and yes my old Opteron 2218 do not have L3 cache to share.
and yes not all systems do have super-linear-speedup
"A single die will only have 6 cores"
how cares ?
"The rest are connected in HT mesh just like multi socket systems."
oh wow... nothing new here.. if the HT links are fast you can get nearly the same speed as nativ cores ;-)
"Your non-linear scale is up to 6 cores for now. "
no!.. the nonlinear speed up grow up more and more if you have more and more cpus on the same system.
for linux limit is 4096 cores!
only feature is needet is the cpu's share the RAM channels and L3 cache over the HT-Links.
IBM power7 does the same and power7 do have much more than 100% in scale!
"Please no more rocket speed jokes"
its not a joke there are some CPUs with the ability of Super linear speed-up
in my knowledge its the IBM power7 and the Opteron6000 and the newest intelcorei7 based xeon.
Even Intel's superior QPI can't claim 'native speed', accessing neighbor die's L3/IMC via QPI is about the same speed as using a FSB in older generation.
It is you who need to do some home work before you talk out of your dreams. Two die communicate via HT/QPI is about twice slow as accessing local L3/IMC, that doesn't include L3 snooping.
AMD can reduce snooping traffic by denoting 1/2MB of it's 6MB L3 as directory cache, but that also comes with a price of reduced overall cache capacity.
Overall, dreaming of a 2 die x 6 core package performs same as a native 12 core is not likely to happen soon