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Thread: Future Fusion Architecture

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  1. #1
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    Default Future Fusion Architecture

    A question for bridgman, agd5f, airlied, glisse, ...

    Just saw a presentation about Future Fusion Architecture, and specifically was triggered by the stuff about memory and MMU.
    Does this mean that in the future GEM/TTM will become unnecessary?

  2. #2
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    I expect we will always need something like GEM/TTM if only to allow common userspace code to be shared across multiple hardware vendors and older generations of hardware. The implementation should get easier on newer hardware, however, and some functions could possibly become no-ops rather than complex operations.

  3. #3
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    Quote Originally Posted by bridgman View Post
    I expect we will always need something like GEM/TTM if only to allow common userspace code to be shared across multiple hardware vendors and older generations of hardware. The implementation should get easier on newer hardware, however, and some functions could possibly become no-ops rather than complex operations.
    awesome. thanks!

    sure hope that the HW does cache coherency though, otherwise you're screwed

    finally x86 is moving in a sensible direction. we did this already in '96 with MIPS R3000 SoCs

  4. #4
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    Also, any idea how long it might take to get the register/assembly specs through? Since this is a much greater change from VLIW5->4, I could see it taking a while...

  5. #5
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    Quote Originally Posted by Chad Page View Post
    Also, any idea how long it might take to get the register/assembly specs through? Since this is a much greater change from VLIW5->4, I could see it taking a while...
    the next fusion 2012 fusion2.. is the (hd6900) VLIW 4D architecture.

    or do you mean the "r900" next gen gpu architecture? its fusion3 2013...

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