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Thread: Gallium3D OpenCL GSoC Near-Final Status Update

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  1. #17
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    Oct 2007


    Quote Originally Posted by Qaridarium View Post
    why not call it VLIW+SIMD to RISC+VLIW or CISC+VLIW.
    That would be even more confusing, if such a thing is possible

    Seriously, GPU instructions have always been much closer to RISC than CISC, especially ATI/AMD GPUs. They're all single-clock, and there are relatively few instructions -- lots of opcodes but those are mostly subtle variants of the same basic function (eg 6.02*10^23 different compare operations).

    One could argue that VLIW RISC and CISC are both "complex" from a sufficiently abstract point of view but I don't think they are generally regarded as interchangeable. The transition really is from VLIW RISC to non-VLIW RISC.

    Quote Originally Posted by Qaridarium View Post
    i think the r900 will be 1 RISC core instead of a VLIW core and 5 SIMD cores added to the RISC core and maybe an firmware layer to CISC to protect the internal chip logic.
    The slides presented at AFDS talked about 1 scalar unit plus 4 SIMDs (sometimes called vector ALUs) per compute unit (CU) - see pdf for session 2620 at :

    I think it's fair to say that the instruction sets for both scalar and vector units can be considered RISC, just like the instruction set for the VLIW core, but the RISC vs CISC topic is almost as dangerous and open to debate as religion or coding standards.

    The whole discussion is made more complicated because we used to talk about "vector operations" (eg the RGBA components of a pixel) being handled in a single vector instruction on 3xx-5xx GPUs or by using 4 of the VLIW slots on a 6xx-Cayman GPU. With GCN and beyond "vector" is being used the other way, referring to the 16 elements of the SIMD as a vector.

    That's why the SIMD aspect seems new -- VLIW was visible to the programmer while SIMD was not, so it got talked about the most. Now that VLIW is out of the picture SIMD is the most visible thing, and we have to talk about it because a CU contains SIMDs *and* a scalar engine, so the natural terminology is "vector" for the SIMDs and "scalar" for the... um... scalar engine.

    What we call a SIMD used to work on a 16x4 or 16x5 array of data, now it works on a 1D vector of data.

    But it's still RISC
    Last edited by bridgman; 08-20-2011 at 01:43 PM.

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