AMD FX-4100 Bulldozer

[duby229]

This is a strange form of logic. What does benchmarking have to do with anything? We don't call Sandy Bridge a 25 core chip just because it performs 25 times faster than a 486DX. (Just a random number there, I'm not sure what the actual comparison would be). We look at the actual hardware and what it provides, not benchmarks.

Probably closer to a thousand...

[duby229]

if you have the double long pipe line software emulated(hyper-threating) splits into 2 pieces )intel i3( its the same compared to 2 half long pipe lines.
because of this the benchmarks nearly the same.
Intel wins if more single threated performance is needed and amd wins if more multi-task performance is needed.
and i don't have to read your posts again because your posts chance nothing about my argumentation.

You really have no idea what your talking about.

Both architectures are superscaler. But in all reality the full pipe including frontend and FP is probably longer on BD than it is on SB. BD almost certainly has more stages in its pipeline than SB has... Its longer and narrower.

You need to google what a superscaler pipeline is.

here are links to wikipedia...
http://en.wikipedia.org/wiki/Superscalar
http://en.wikipedia.org/wiki/Instruction_pipeline

[deanjo]

Probably closer to a thousand...

Well runs about 110x "faster", the number of executions it can do at that clock frequency however is an entirely different matter. ;D

[Qaridarium]

This is a strange form of logic. What does benchmarking have to do with anything? We don't call Sandy Bridge a 25 core chip just because it performs 25 times faster than a 486DX. (Just a random number there, I'm not sure what the actual comparison would be). We look at the actual hardware and what it provides, not benchmarks.

it was just an analogy. but an single core from the intel i3 isn't a single calculation unit there are many calculation units in this core this many units just emulate a single-core.

[Qaridarium]

You really have no idea what your talking about.

Both architectures are superscaler. But in all reality the full pipe including frontend and FP is probably longer on BD than it is on SB. BD almost certainly has more stages in its pipeline than SB has... Its longer and narrower.

You need to google what a superscaler pipeline is.

here are links to wikipedia...
http://en.wikipedia.org/wiki/Superscalar
http://en.wikipedia.org/wiki/Instruction_pipeline

i already know this. its a multiple group of calculation units which emulate a single core.

because of this you are wrong because the intel core i3 do have more internal calculation units per real "core"

amd FX4000 there are 2 modules a module so have 2 cores and every core do have 2 internal calculation units=8 calculation units
and on Intel side 4 internal units emulate 1 core and there are 2 of them=8calculation units.

if you calculate it both of them the i3 and fx4000 do have 8 internal calculation units.

[AlbertP]

Let's first make a good definition for "core" before continuing to argue this way.

[bridgman]

But the argument is about what constitutes a "core". If they agree on that then there won't be anything to argue about

The problem is that we're really arguing about rounding artifacts here. A hyperthreading core has some dedicated resources for each thread but sufficiently few that most people round it down to "one core". A CMT module has relatively more dedicated resources for each thread, enough that most people round it up to "two cores". Both simplifications are imperfect, and you really need to go down at least one more level of detail (to the individual execution units after the decoder) before everyone can agree on the terms.

The good news is that the thread is heading in that direction, but so far it's only talking about integer ALU execution units and not the other execution units (load/store etc..).

[AlbertP]

Yes, but a CPU of today is a very complicated thing. At least it is compared to the single-core Athlon XP in my desktop, which has already a lot of transistors.

[bridgman]

Yep, although one could argue that the big jump in complexity happened a few years before your Athlon XP came out.

My rule of thumb is that whenever you talk about "instructions per clock" rather than "clocks per instruction" you're talking about seriously complex designs

[duby229]

Please dont tell me that AMD is trying to move towards a "clocks per instruction" model.... That would be bad....

De-emphasizing ILP was bad enough.

I dont really like the term IPC, I think ILP is a more adequate term to use for what we are talking about.