CISC and RISC does not mean Complex or Simple Instructions, actually means Complex or Reduced Instruction-Set, that means Complex or Reduced relations between Instructions. So on RISC, Instructions are relative between them, that means the one is a little the other and goes on. So RISC can execute all kinds of Instructions (float,integer,...) by the same units --and-- with the same way, while the ugly CISC cannot. All the above means that RISC wants 1-Million-Transistor without cache for 2.5dmips/mhz while CISC wants 20m, also the difference goes to 40/1 for Stream-Processing like Gaming. Finally CISC does not translating or decoding anything to internal RISC, decoding for processors its a totally different thing, CISC to RISC is recompiling and its the reason for Intel to insist on x86, because it was difficult to emulate a CISC on a RISC or another ISA CISC. But that is in the past:
http://en.wikipedia.org/wiki/Loongson See this in LC3-part: 2*512bit(fmac) vectors for Float and another same length unit for Integer (bigger against Ivy Bridge). Also has Emulation-Instructions and Mips3D-Instruction, in order to accelerate Qemu and Software-Rasterizers like LLVMpipe, and its not the smallest of the RISC processors (16cores@2ghz=20watt). Don't invest on Intel, Amd, Nvidia, Microsoft, Apple, Adobe, Unreal,...