
Originally Posted by
artivision
The L3C part (2013) will have 1024bit-Fmac for floating point and another similar length for integer, that is 12-15 dmips/mhz wile Ivybridge is 9.5. All this with a consumption less than an Atom, 43m transistors per core vs 47mt of an Atom. Also Mips can have a less complex 512bit-Fmac (2.5drystone) interface, with 1mt logic and 1,5mt L1 memory, make that 4mt with integrated 3D instructions and shared cache. So i prefer an L3C@2.5ghz-28nm instead of an 1.5-2ghz Atom-32nm, its 5-6 times faster and 3.5-4 times on x86 emulation mode. Also Intel is giving 20mt per 256bit-Fmac graphics and in the future probably 10mt, Mips and probably others can do that with 1/5 the transistors and with just a software rasterizer. So if you have 16 small cores with 32 instructions and 2.5ghz you have 1.3tflops.