Tilera Publishes TILE-Gx CPU Back-End To LLVM

[phoronix]

Phoronix: Tilera Publishes TILE-Gx CPU Back-End To LLVM

After already having integrated TILE-Gx support into GCC 4.7, Tilera is now calling for the mainlining of its TILE-Gx back-end into LLVM. The LLVM Tile-Gx back-end is needed for the company's forthcoming many-core processor...

http://www.phoronix.com/vr.php?view=MTMxNTk

[F i L]

Can anyone give a simplified explanation as to the difference between this CPU architecture and the Parrallella?

[shaunehunter]

The Parallella is an ARM processor with 16 or 64 FPU's and the TileX has it's own ISA and each core is a complete superscalar CPU.

[bms20]

The Parallella is an ARM processor with 16 or 64 FPU's and the TileX has it's own ISA and each core is a complete superscalar CPU.

Wasn't one of the Tilera processors based around many MIPS cores?

Is this one similar or is it a totally different ISA?

[shaunehunter]

Wasn't one of the Tilera processors based around many MIPS cores?

Is this one similar or is it a totally different ISA?

The microcode was described as MIPS like in a couple news stories but it's a VLIW processor. MIPS doesn't have them listed as a licencee either.