Intel Posts Latest AVX10.1-256 & AVX10.1-512 Compiler Patches For GCC

Since announcing AVX10 earlier this year, Intel compiler engineers have been quite busy preparing the open-source compiler toolchains like GCC and LLVM/Clang for this next iteration of Advanced Vector Extensions. On Thursday night the latest AVX10.1 work was posted for the GNU Compiler Collection ahead of its upcoming feature freeze.

For a few months now Intel's been pushing AVX10 support into GCC along with preparations for the Advanced Performance Extensions (APX). The newest GCC patch overnight from Intel is "[PATCH] Initial support for AVX10.1."

This new patch is what goes ahead to now add the compiler options for "-mavx10.1", "-mavx10.1-256", and "-mavx10.1-512" compiler options. It also adds the respective "-mnoavx10.1" options. Plus it adds other plumbing around toggling of AVX10.1 / AVX10.1-256 / AVX10.1-512 support within the GCC compiler code.

With that patch came a separate message explaining their latest AVX10 compiler planning:

Our proposal is to take AVX10.1-256 and AVX10.1-512 as two "virtual" ISAs in the compiler. AVX10.1-512 will imply AVX10.1-256. They will not enable anything at first. At the end of the option handling, we will check whether the two bits are set. If AVX10.1-256 is set, we will set the AVX512 related ISA bits. AVX10.1-512 will further set EVEX512 ISA bit.

It means that AVX10 options will be separated from the existing AVX512 and the newly added -m[no-]evex512 options. AVX10 and AVX512 options will control (enable/disable/set vector size) the AVX512 features underneath independently.

At least Intel continues to be quite punctual in their open-source compiler work and getting out new ISA features and CPU family targets added to the upstream compiler code-bases well in advance of product launches. So by the time we're actually seeing AVX10.1 (or more excitingly, AVX10.2) enabled processors in the wild, all of the open-source compiler support will ideally be all sorted out and in released versions.