Intel Begins Posting GCC Compiler Patches For AVX10.1

Last month Intel announced APX and AVX10 as the successor to AVX-512 that will see both P and E cores in the future supporting this updated Advanced Vector Extensions implementation. Delightfully, today Intel engineers began posting GCC compiler patches for beginning to enable AVX10 support.

Just weeks after Intel publicly announced AVX10 as a feature that will first see initial support with Xeon Scalable "Granite Rapids" processors, their engineers have started posting the code to enable this ISA extension within the GNU Compiler Collection.

"We will send out our initial support of AVX10 and some sample patches in this mailing thread. And there will be more coming up afterwards. Therefore, we would like to share our proposed AVX10 design in GCC.

Here is a quick introduction to AVX10:
- AVX10 is the first major new ISA since the introduction of AVX512 in 2013.
- Since the introduction of AVX10, we would like to establish a common, converged vector instruction set across all Intel architectures, including Xeon Server, Atom Server and Clients.
- The default maximum vector size for AVX10 will be 256 bit, while 512 bit is optional.
- AVX10.1 will include all existing AVX512 instructions in Granite Rapids.
- There will be no new AVX512 CPUID introduced in future. All EVEX vector instructions will be under AVX10 umbrella.
- AVX10 will be version-based ISA instead of tons of different CPUIDs like AVX512BW, AVX512DQ, AVX512FP16, etc.
- Based on AVX10.1, AVX10.2 will introduce ymm embedded rounding, SAE (Suppressed All Exceptions) control and new instructions."

Intel has been promoting the fact that existing AVX2-compiled software can be easily rebuilt for AVX10 and should yield better performance. AVX10 is also extremely important since their future E cores will support it and thus finally allowing improved AVX support with future Intel Core client processors as well as E-core-only server platforms.

The proposed compiler options around AVX10 currently consist of:

- -mavx10.x: The option will enable AVX10.1-AVX10.x features with a default 256 bit vector width to make sure the compatibility on all platforms.
- -mavx10.x-512: The option will enable AVX10.1-AVX10.x features with 512 bit vector width. “-mno-avx10.x-512” option will not be provided to avoid confusion of disabling 512 vector width or avx10.x itself.
- -mavx10.x-256: The option will enable AVX10.1-AVX10.x features with 256 bit vector width. But it will disable 512 bit vector width since the vector size is indicated in option. “-mno-avx10.x-256” option will not be provided to
keep align with the 512 ones.
- -mno-avx10.x: The option will disable all the features introduced >=avx10.x (both 256 and 512 bit) and keep features <avx10.x if enabled, just like how -mno- options behave previously.

The AVX10.1 enablement work for GCC is also preparing to transition the Granite Rapids and Granite Rapids D compiler targets over to "AVX10.1/512" compared to the current AVX-512 ISA target.

See this mailing list thread for the initial patches and discussion likely to happen around AVX10 support for the GCC compiler. Given the timing and still being some months before GCC 14 enters the next stage of development, the initial AVX10.1 support will hopefully land in time for next year's GCC 14.1 stable release. It's nice as always seeing Intel's early work around new CPU ISA features for the GCC (and LLVM Clang) open-source compilers.