Intel Xeon Sapphire Rapids Code Continues Landing For Coreboot

More Intel 4th Gen Xeon Scalable "Sapphire Rapids" code was merged this weekend into Coreboot as part of enabling this latest generation Intel server platform to enjoy this open-source system firmware solution when paired with the necessary Intel FSP binaries.

As noted back in January following the official Sapphire Rapids launch, Intel is working on supporting Coreboot for these latest processors and as part of that also bringing up their dual socket "Archer City" reference motherboard made by Quanta Computer. Besides the nuisance around the FSP binaries, it's still a matter of seeing what server motherboard vendors will end up supporting Coreboot on their platforms or what server motherboards end up seeing unofficial ports to Coreboot. There has been talk of possibly some Supermicro motherboards seeing Coreboot support but aside from that much of the vendor interest in Coreboot tends to satisfy the wishes/needs of the major hyperscalers like Meta and Google.

The latest Coreboot code merged on Sunday for Sapphire Rapids is adding the ramstage code, "it implements SPR ramstage including silicon initialization, MSR programming, MP init and certain registers locking before booting to payload." As part of that is also new header files and romstage code, some of which is similar to Coreboot's Intel Cooper Lake code.

The latest ongoing Sapphire Rapids enablement work for Coreboot can be tracked via this GitHub search. Here's to hoping we see some interesting Intel Xeon Scalable motherboards deciding to support Coreboot along with the ongoing effort for more flexibility around Intel's FSP binaries.