GCC Compiler Gets Tuned Up For MIPS' M51xx

Within the latest GCC developer code is better support for Imagination's MIPS M51xx M-Class CPU family.

The MIPS M51xx is Imagination's entry-level Series 5 Warrior M-class CPU cores. The M51xx consists of two processor cores and are superset extensions of the MIPS microAptiv family, as explained on the Imagination Tech web-site. This MIPS Release5 Architecture processor family is designed for embedded applications ranging from IoT to automotive to wearables. The hardware was announced back in 2014.

Landing in SVN/Git this morning for GCC is scheduling support for the M51xx core family (with new -march options for m5100 and m5101)as well as support for the -march=interaptiv switch, which in turn maps to GCC's existing -mips32r2. These latest MIPS contributions to GCC were done by an Imagination Technologies engineer.