With the R600g LLVM back-end the register pressure scheduler has now been replaced by the VLIW (Very Long Instruction Word) scheduler. The VLIW scheduler for supporting the Radeon HD 2000 through HD 6000 series graphics cards is far from being ideal in terms of being optimally efficient as it ignores some complicated instructions right now, but it should be an improvement over the status quo.
According to Tom Stellard, the AMD employee that has been working on open-source OpenCL as of late for Gallium3D, reports that switching to the new scheduler resulted in a 50% performance boost for a SHA1 compute shader test. However, he has yet to see the performance impact of the VLIW scheduler on complicated graphics shaders.
From the commit:
It's not optimal, but it's better than the register pressure scheduler that was previously being used. The VLIW scheduler currently ignores all the complicated instruction groups restrictions and just tries to fill the instruction groups with as many instructions as possible. Though, it does know enough not to put two trans only instructions in the same group.It looks like it's time for me to start some new R600g benchmarks!
We are able to ignore the instruction group restrictions in the LLVM backend, because the finalizer in r600_asm.c will fix any illegal instruction groups the backend generates.
Enabling the VLIW scheduler improved the run time for a sha1 compute shader by about 50%. I'm not sure what the impact will be for graphics shaders. I tested Lightsmark with the VLIW scheduler enabled and the framerate was about the same, but it might help apps that use really big shaders.