Kernel Developers Begin Work On CPPC Processor Performance Controls

Ashwin Chaugule of Linaro has announced his experimental kernel implementation of Collaborative Processor Performance Controls (CPPC) that is part of the ACPI 5.1 specification.

An increasing amount of x86 and ARM64 hardware is expected in the marketplace soon that supports CPPC, which is a new interface for CPU performance control between the OS and platform, while right now it's just exposed by a limited number of systems. Here's more from Ashwin's description:

CPPC is the new interface for CPU performance control between the OS and the platform defined in ACPI 5.0+. The interface is built on an abstract representation of CPU performance rather than raw frequency. Basic operation consists of:

* Platform enumerates supported performance range to OS

* OS requests desired performance level over some time window along with min and max instantaneous limits

* Platform is free to optimize power/performance within bounds provided by OS

* Platform provides telemetry back to OS on delivered performance

The Collaborative Processor Performance Control work published is largely just a starting point and to initiate discussion about implementing this CPU performance-controlling feature. Those interested in learning much more can read this lengthy email post.