GNU Toolchain Begins Landing RISC-V Bitmanip/Zbs Instructions Support

[phoronix]

Phoronix: GNU Toolchain Begins Landing RISC-V Bitmanip/Zbs Instructions Support

The GNU toolchain (initially with the GNU Assembler) has begun landing support for RISC-V's Zbs instructions that are part of the Bitmanip extension to the processor ISA...

https://www.phoronix.com/scan.php?page=news_item&px=GNU-Prepares-For-Bitmanip-Zbs

[andreano]

In draft 0.94 from January, I saw one killer feature: cmov

There were some other branchless goodies, like min and max, but in RiscV, where part of the performance is supposed to come from how simple it is for the processor to combine consecutive instructions into larger ones, you only really need cmov for branchless.

And now (as of 1.0.0), they removed cmov. I don't get it.

[discordian]

In draft 0.94 from January, I saw one killer feature: cmov

There were some other branchless goodies, like min and max, but in RiscV, where part of the performance is supposed to come from how simple it is for the processor to combine consecutive instructions into larger ones, you only really need cmov for branchless.

And now (as of 1.0.0), they removed cmov. I don't get it.

Cmov is a completely class of instruction-type, normally you can drop the output register as reference since it is overwritten. Here you might depend on the value. It reads one more register than anything else is another way to look at it.

It will have costs everywhere, blowing up cost for small implementations and not helping a big deal if you have a a fat ooo core.
So I welcome doing the reasonably thing and add instructions that remove alot of branches while being the normal 1/2 register read and 1 register write.

[andreano]

It reads one more register than anything else

Yeah, 3 inputs. I read something along those lines – 3 read-lines out of the register file was too much for some. But isn't that just one way to do it? They could "just" have made a cmov with 2 inputs, which would be 99% as useful, and might be implemented via conditional register writeback. Which in my naive mind sounds simpler and more energy efficient*. It might make more sense the more predicated instructions you have (including fused ones that don't exist in the ISA).

*If the Landauer limit is any indication, the lowest limit of energy a computation can use is only given by how many bits you overwrite.

[discordian]

It's just one of the downsides, these kinda instruction just need some special sauce. Cmov doesn't fit with the rest of the new instructions to say the least.
It's probably similar to just do special handling if you have a conditional jump over a single instruction. (Always execute the ins, just conditionally skip the write-back). doesn't affect the instruction set, and it is a cmov equivalent.

[carewolf]

And cmov is just slower than branches. They are sort of deprecated outside of SIMD code