GCC 13 Adds RISC-V T-Head Vendor Extension Collection

[phoronix]

Phoronix: GCC 13 Adds RISC-V T-Head Vendor Extension Collection

Being merged today into the GCC 13 compiler is the set of T-Head vendor extensions to the RISC-V ISA. This set of vendor extensions is designed to augment the RISC-V ISA and provide faster and more energy efficient capabilities...

https://www.phoronix.com/news/GCC-13-Adds-RISC-V-XThead

[willmore]

Do these map to any proposed or standard RISC-V instructions or is this completely a T-Head only thing? Coming from the context of the C906 used in the BL808/Ox64, I'm curious if any of the extensions of that core are getting closer to mainline gcc.

[ayumu]

Do these map to any proposed or standard RISC-V instructions or is this completely a T-Head only thing? Coming from the context of the C906 used in the BL808/Ox64, I'm curious if any of the extensions of that core are getting closer to mainline gcc.

I understand extensions that aren't ratified have to live in encoding space reserved for custom extensions, where multiple vendors can overlap the same encodings.

[zexelon]

If RISC-V ever takes off its going to be hell to figure out what to buy with all these "extensions" for different bits and pieces!

Just looking over all the different extension categories leads me to think the base RISC-V is the first realization of the single instruction arch

My guess is in reality probably most of these options will vanish into obscurity in 10 years and what will be left will be a base set standardized on by all the RISC-V foundries.

[coder]

If RISC-V ever takes off its going to be hell to figure out what to buy with all these "extensions" for different bits and pieces!

I thought there were already some profiles defined, or something like that.

That will indeed be key for server/cloud usage.

[willmore]

I understand extensions that aren't ratified have to live in encoding space reserved for custom extensions, where multiple vendors can overlap the same encodings.

That's what I've heard elsewhere. At least the prototype code space is a known unknown. Instead, T-head used the space reserved for the final extension. Which is not the cool way to go about it. ;( Thanks for the insight.

[netkas]

I thought there were already some profiles defined, or something like that.

That will indeed be key for server/cloud usage.

You right, you will have processors with profiles
For example:
RVA20U64 ( Risc-V Application profile 20 for Userspace 64-bit mode) which is basically RV64GC with few more extensions
or
RVA22U64 which is basically ( simplifying things) RVA20U64 + BitManip

[OrenJMaurice]

Not knowing very much about RISC-V yet, and given it'll have a very diverse set of instruction sets, by all I see here, does it have any "emulation instrumentation" baked in, so adding support for a specific instruction-set, in software, will be efficient ?