LLVM 17 Adds New ISA Support For Intel Arrow Lake S & Lunar Lake

[phoronix]

Phoronix: LLVM 17 Adds New ISA Support For Intel Arrow Lake S & Lunar Lake

Following GCC recently adding new x86 instructions for Intel Arrow Lake and Lunar Lake, the LLVM 17 open-source compiler has now received similar treatment...

https://www.phoronix.com/news/LLVM-17-Arrow-Lake-ISA-Adds

[Lbibass]

Seems to me that this means those architectures are going to have AVX512 support? Even on the E-Cores? If so, that's great news! avx512 can definitely provide boosts to some workloads.

[mlau]

Seems to me that this means those architectures are going to have AVX512 support? Even on the E-Cores? If so, that's great news! avx512 can definitely provide boosts to some workloads.

seems only avx2; at least the gcc codes for arrow/lunar lake don't indicate any avx512 support.

[AdrianBc]

Seems to me that this means those architectures are going to have AVX512 support? Even on the E-Cores? If so, that's great news! avx512 can definitely provide boosts to some workloads.

No, none of the 3 future Intel CPUs expected to be launched during 2024, Arrow Lake (CPUID model 06_C5H, expected to be made with the Intel 20A CMOS process, for laptops), Arrow Lake S (CPUID model 06_C6H, expected to be made with a TSMC 3 nm CMOS process, for desktops) and Lunar Lake (CPUID model 06_BDH, expected to be made with the Intel 18A CMOS process, for laptops), will support AVX-512.

Nevertheless, all 3 CPUs will support a few of the most useful AVX-512 instructions, e.g. IFMA (for fast big integer multiplications) or instructions for machine learning, but in an alternative encoding which uses the VEX prefix of the AVX instructions, instead of the EVEX prefix of the AVX-512 instructions.

It should be noted that Arrow Lake and Arrow Lake S support different instruction sets. While they might have a very similar microarchitecture, they are made by different chip foundries and only the latter supports most of the instructions that will be supported by Lunar Lake.