Fedora Progresses In Bringing Up RISC-V Architecture Support

[phoronix]

Phoronix: Fedora Progresses In Bringing Up RISC-V Architecture Support

Richard Jones at Red Hat has been working on bringing up RISC-V processor architecture support for Fedora...

http://www.phoronix.com/scan.php?page=news_item&px=Fedora-RISC-V-Progress

[uid313]

Does RISC-V support virtualization?

Does it have any instruction extensions such as SSE or AVX?

[boxie]

Does RISC-V support virtualization?

Does it have any instruction extensions such as SSE or AVX?

Considering you can implement a RISC-V CPU on a relatively small FPGA... probably not

[microcode]

Considering you can implement a RISC-V CPU on a relatively small FPGA... probably not

There are different subsets for different use cases. The very small implementations only have a fully-privileged mode(machine mode), whereas the larger ones have other privilege modes: hypervisor mode, supervisor mode, and user mode.

Does RISC-V support virtualization?

Does it have any instruction extensions such as SSE or AVX?

I think the Hypervisor mode counts as accelerated virtualization.

There is a Packed SIMD extension (like SSE); however there is more interest in extensions providing something like the vector machines pioneered by Cray. Packed SIMD has a lot of issues, not the least of which is that you need to write new compiler passes and optimizations and introduce new opcodes every time a wider SIMD extension comes along. First there was SSE, then SSE2, then SSSE2, then SSE3, then SSE4.1, then SSE4.2 then AVX, then AVX2, then AVX512. With a Cray-style vector machine, the same code can run at full efficiency regardless of how wide the ALUs are, and new code does not need to be written in order to gain performance from wider vectors.

It's quite exciting, and now that the Privileged ISA Spec is solidifying, we can start to see big Linux/BSD-running application processors in addition to the microcontrollers and embedded cores which are already shipping with RISC-V.

[arakan94]

Does RISC-V support virtualization?

Does it have any instruction extensions such as SSE or AVX?

It's clean design, incompatible with i386/amd64 architecture. And it's also quite interesting architecture. SSE/AVX alternative is variable vector extension - also interesting idea.

[starshipeleven]

Considering you can implement a RISC-V CPU on a relatively small FPGA... probably not

Hello? You can have RISC-V microcontrollers too (just as you can have x86 ones), the ones on the small FPGA are the controllers.

[Snaipersky]

Clean ISA is OK - but a more complex ISA might lead to better performance.

Latest papers I saw showed BOOM chips outperforming ARM in both IPC and power draw.

[arakan94]

Clean ISA is OK - but a more complex ISA might lead to better performance.

Might.. But the idea of whole RISC philosophy is to do exact opposite - make it as simple as possible. Simple design can run on higher frequency without lengthy optimizations and is easily expandable. My only worry with this design is how they approach conditionals and performance hit they take with them.

But code with few conditions will probably run way more efficiently than anything Intel or ARM can offer..

[hajj_3]

nvidia is designing a risc-v chip to replace the one on their graphics cards that is used for I/O and other such things. They are also going to integrate it into their tegra chips. They did a talk video about this at some conference recently.

[jabl]

If you define a risc ISA as a load - store ISA, and all else equal, then yes, sure. But of course, everything else is not equal. For instance, if you're comparing risc-v vs x86, an obvious difference is that risc-v is a three - operand isa whereas x86 is a two - operand one.

Iirc the compressed instruction encoding extension makes risc-v denser than x86-64 on a number of benchmarks.