Ampere-1A CPU Support Added To GCC 13

Leading AArch64 server processor vendor Ampere Computing announced this summer AmpereOne as the branding for their next-generation AArch64 "cloud native" server processor design succeeding their current Ampere Altra / Ampere Altra Max processors based on Neoverse-N1. While the AmpereOne processors have yet to be formally launched, with the new AArch64 core being an original design, Ampere Computing has already been submitting support patches to the open-source compilers. The latest twist in this enablement is now acknowledging a new "Ampere-1A" variant.

Going back to last November was adding the "Ampere1" target to GCC that confirmed the next-generation Ampere Computing server processor is using an ARMv8.6-based ISA and other basic features. Earlier this year LLVM support was added as Ampere1.

Now being merged for GCC 13 is also introducing "ampere-1a" as a new CPU target. Ampere-1A has an updated instruction cost table, a new fusion pair (A + B + 1 and A - B - 1) and has a different processor ID to Ampere-1 (non-A). Unlike Ampere-1, Ampere-1A does support AArch64's Memory Tagging Extension (MTE).

Prior to seeing this GCC commit made earlier today, I don't believe I've heard of this "Ampere-1A" variant at all, so it will be interesting to see how it ends up being positioned and what other differences it may have over the standard AmpereOne core. It's certainly possible Ampere-1A may be some sort of AmpereOne refresh not launching until after the upcoming AmpereOne product launch but the compiler patches published now in order to make it into this next annual GCC compiler version (if so, kudos to Ampere Computing for getting out the new enablement patches early). In any event we are certainly eager to hear more about AmpereOne in general for this AArch64 server processor to compete with AMD EPYC Genoa and Bergamo along with forthcoming Intel Xeon Sapphire Rapids.