LLVM Merges Support The For Tenstorrent TT-Ascalon-D8 RISC-V CPU

Adding to the interesting code building up for next spring's release of the LLVM 20 compiler stack is having the Tenstorrent TT-Ascalon D8 as the newest RISC-V processor target.

Tenstorrent TT-Ascalon architecture is a high performance, scalable RISC-V design from a 2-wide to 8-wide implementation with the "D8" code upstreamed for LLVM 20 being around the 8-wide implementation.

Tenstorrent is hoping the TT-Ascalon D8 will be used within servers, laptops, and HPC environments. More details on the TT-Ascalon for those interested via Tenstorrent.com.

As of last week the TT-Ascalon D8 target was merged into LLVM 20 Git. With this newest LLVM code, the Tenstorrent TT-Ascalon can be targeted using the "-mcpu=tt-ascalon-d8" compiler option. This LLVM support for the TT-Ascalon was worked on by Tenstorrent engineers directly.