GCC 10 Lands OpenRISC Support For Floating Point Instructions

When it comes to open-source processor ISAs, RISC-V currently captures much of the spotlight but OpenRISC continues chugging along as another open-source CPU architecture. The OpenRISC GCC compiler back-end and other software tooling also continues to move along for this architecture that's been in the works since 2000.

The OpenRISC back-end/target landed just at the end of 2018 for the current GCC 9 stable series. This OpenRISC "or1k" support continues maturing. It took so long for the OpenRISC support to land into GCC as the original developers of the compiler support wouldn't agree to their copyright assignment to the Free Software Foundation for getting the code merged. As a result, a clean-room rewrite of the GCC OpenRISC code was needed before it could be accepted into GCC.

This weekend, some OpenRISC/or1k improvements hit the development compiler for GCC 10. The culmination of that work is initial support for the FPU. With GCC 10 for OpenRISC, support for hardware floating point instructions are now supported and can be toggled via the "-mhard-float" switch. There is also double-precision floating-point operations as part of the newer OpenRISC 1.3 specification.

While it's great seeing the software progress, unfortunately, there doesn't appear to be too much recent progress in spinning OpenRISC chips for general purpose computing or any convenient developer boards (short of using FPGAs).