Intel Icelake Server Chips To Support WBNOINVD & PCONFIG

The GCC and LLVM/Clang compilers have been working on Icelake CPU support for a while now as just the "icelake" target but now it's being separated into "icelake-client" and "icelake-server" as the CPU feature differences between the desktop-class processors and Xeon server chips become more clear for this succeeding generation to Cannonlake.

We've already reported on AVX-512 coming to all of the Icelake processors with no longer being reserved just for the high-end Intel CPUs. Besides AVX-512 additions, all of the Icelake CPUs will have some new additions like GFNI (Galois Field NI) and UMIP (User-Mode Instruction Prevention) and VAES.

But through the patch work in GCC 8 now being confirmed as new features reserved just for server-class Intel (Xeon) CPUs are PCONFIG and WBNOINVD.

WBNOINVD is used for writing back all modified cache lines from the processor's internal cache back to the main system memory while not invalidating/flushing the internal caches.

PCONFIG meanwhile is a new instruction for configuring platform features and appears in part related to Intel's new memory encryption features.

So at least for now until seeing any new Icelake feature patches, it takes next year's server chips to having: MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG, and WBNOINVD.

I'm quite looking forward to Icelake especially with these chips rumored to be the first with in-chip mitigation of Spectre and Meltdown, but before then we still need to get to the Cannonlake rollout.