Mesa Fixes Up The Recent L3 Cache Pinning Rework
Written by Michael Larabel in Mesa on 4 May 2021 at 06:26 AM EDT. Add A Comment
MESA --
Going on for a few years now has been some Mesa optimizations for AMD Ryzen CPUs and in particular L3 cache optimizations. There is now a fix to re-enable this support after it was mistakenly broken earlier this year.

Back in March and back-ported to stable with Mesa 21.0.2 was an effort to improve the AMD L3 cache calculation code. This was due to the prior code breaking on dual socket AMD EPYC systems checked, but it turns out that fix was broken itself.

AMD developer Marek Olšák landed a fix today in Mesa 21.2-devel and will be back-ported to Mesa 21.0/21.1 to re-enable the L3 cache pinning behavior.

Marek noted in the commit that fixes the L3 code from March, "fix (re-enable) L3 cache pinning. cores_per_L3 was uninitialized, so it was always disabled. Remove the variable and do it differently." Whoops, at least it's fixed now.
Related News
About The Author
Author picture

Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 20,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter or contacted via MichaelLarabel.com.

Popular News This Week