Western Digital To Open-Source The "SweRV" RISC-V Core In 2019
Written by Michael Larabel in Hardware on 5 December 2018 at 05:08 AM EST. 26 Comments
HARDWARE --
More than a year ago Western Digital talked up how they would begin designing RISC-V cores and shipping them in devices and that is indeed panning out. The company has unveiled their new SweRV core and plans to open-source it in 2019.

At the RISC-V Summit, Western Digital talked about their continued investment into this royalty-free, open-source processor ISA. Their current RISC-V design is dubbed SweRV and is a 32-bit, 2-way super-scalar design that features a 9-stage pipeline core and clocks up to 1.8GHz and manufactured on a 28nm process. Western Digital plans to use SweRV within flash controllers / storage devices and other embedded designs.

In the first quarter of 2019, Western Digital intends to open-source the SweRV core design to the community. Western Digital is also providing the SweRV ISS (Instruction Set Simulator) as open-source to help with design and validation.

More details on SweRV and the company's RISC-V efforts can be found at WesternDigital.com.
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Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 10,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter or contacted via MichaelLarabel.com.

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